1. Field of the Invention
The present invention relates to an image signal processing apparatus which takes in the output of an image pickup device, conducts various processing operations, and then outputs an image signal having a predetermined format.
2. Description of the Related Art
An imaging device such as a TV camera using a CCD image pickup device is provided with a CCD driver for driving the CCD, a timing control circuit for controlling the operation timing of the CCD, and a signal processing circuit for conducting various processing operations in accordance with an output of a CCD to obtain a predetermined image signal. This kind of signal processing circuit is mainly constituted of a sample and hold circuit for sampling the output of the CCD, an automatic gain control circuit for constantly maintaining an average level of a signal, and a gamma correction circuit for causing the signal level on the reproduction side of an image to correspond to non-linear properties of a luminous brightness of a CRT.
FIG. 1 is a block diagram illustrating the constitution of a conventional imaging device, and FIG. 2 is a timing diagram illustrating its operation.
A CCD image pickup device 1 of a frame transfer type is constituted of an imaging area I, a storage area S, a horizontal transfer area H and an output section D. The imaging area I comprises a plurality of shift registers continuously arranged in a mutually parallel state in a vertical direction, and each bit of these shift registers is potentially sectioned by the function of electrodes to define a plurality of light receiving picture cells. The storage area S comprises a plurality of shift registers in succession to the respective shift registers of the imaging area I, and it receives and stores information charges from the shift registers of the imaging area I. The horizontal transfer area H comprises a single shift register in which each bit is caused to correspond to an output terminal of each shift register of the storage area S and it successively transfers and outputs the information charges received from the storage area S. The output section D is arranged on the output side of the horizontal transfer area H, and it converts the information charges output from the horizontal transfer area H into voltage values and outputs them. The imaging area I, the storage area S and the horizontal transfer area H of the CCD image pickup device 1 are connected to a V driver 2, an S driver 3 and an It driver 4, respectively. The V driver 2, the S driver 3 and the H driver 4 operate in accordance with a common reference clock. For example, the imaging area I and the storage area S are fed with four-phase transfer clocks .phi.v and .phi.s, respectively, and the horizontal transfer area H is fed with a two-phase transfer clock .phi.H. In consequence, the information charge generated in the imaging area I of the CCD image pickup device 1 is first transferred from the imaging area I to the storage area S every one screen, in accordance with a frame transfer clock. Next, the information charge is transferred from the storage area S to the horizontal transfer area H every one horizontal line in accordance with a line feed pulse. Afterward, the information charge is further transferred from the horizontal transfer area H to the output section D in accordance with a horizontal transfer clock.
A CCD output taken out from the output section D of the CCD image pickup device i is subjected to various treatments such as sampling, amplification and gamma correction, in a signal processing circuit 5, and it is then output as an image signal to an external apparatus.
A timing control circuit 6 comprising a counter and a decoder receives a horizontal synchronizing signal H-SYC and a vertical synchronizing signal V-SYC, and motivates the V driver 2, the S driver 3 and the H driver 4 at a predetermined timing. That is to say, the timing control circuit 6 is reset by the horizontal synchronizing signal H-SYC, and a timing pulse of one horizontal scanning period for starting the S driver 3 and the H driver 4 is produced on the basis of an output of an H counter for counting a clock of a constant cycle and counting up in one horizontal scanning cycle. Then, the timing control circuit 6 is also reset by the vertical synchronizing signal V-SYC, and a timing pulse of one vertical scanning cycle for starting the V driver 2 and the S driver 3 is produced on the basis of an output of a V counter for counting the horizontal synchronizing signal H-SYC and operating in one vertical scanning period. Simultaneously, a sampling pulse, a clamp pulse and the like, which are required in the signal processing circuit 5, are produced so as to coincide with the operation timing of the CCD image pickup device 1, and then fed to the signal processing circuit 5.
In addition to the frame transfer clock, a discharging clock for discharging the information charge of the imaging area I therefrom is given to the imaging area I at timing earlier than the frame transfer clock, and a period from the discharging clock to the frame transfer clock is an exposure period of the CCD image pickup device 1. That is to say, in the CCD image pickup device 1 which always receives light, the information charges stored in the imaging area I are discharged to reset the imaging area I to a stored charge state of O, and after a predetermined period. A newly stored information charge is then transferred and output, whereby the exposure period is set every one screen. Techniques for setting this exposure period are disclosed in, for example, Japanese Patent Application Nos. 157369/1989 and 183976/1989 filed by the same applicant as in the present application.
In the case of the imaging devices typified by TV cameras with a video and the like, miniaturization and weight-saving are desired, and it is one important theme to decrease the number of parts constituting each device. In particular, the decrease of the number of elements constituting each circuit is effective to simplify wiring and to miniaturize a circuit substrate, and hence for the integration of peripheral circuits of the CCD image pickup device 1, various measures have been taken.
However, the signal processing circuit 5 is constituted of a bipolar transistor circuit capable of easily causing a linear operation in accordance with an analog signal, whereas the timing control circuit 6 and a circuit for generating the horizontal synchronizing signal H-SYC and the vertical synchronizing signal V-SYC are each constituted of an MOS transistor circuit suitable for a pulse operation. Therefore, as peripheral circuits for the CCD image pickup device 1, there are required a circuit block comprising an MOS transistor for receiving clocks to generate various kinds of pulses, and a circuit block comprising a bipolar transistor for receiving a CCD output to output an image signal. As described above, the two kinds of circuit blocks are formed as the different integrated circuit chips, respectively. Consequently, in constructing the imaging device using the CCD image pickup device 1, at least two chips are mounted in addition to the CCD image pickup device 1.
Furthermore, in the output section D of the CCD image pickup device 1, the storage and the output of the information charges are repeated in compliance with the transfer operation of the horizontal transfer area H. Therefore, a CCD output which is output from the CCD image pickup device 1 alternately repeats a reference level (a voltage level in an information charge-free state) and a signal level (a voltage level corresponding to tile stored information charges) at a cycle corresponding to the operation of the output section D. Thus, in the signal processing circuit 5, sampling is carried out so as to take in only the signal level portion alone. However, the reference level becomes unstable sometimes, under the influence of noise generated in the output section D or the sample and hold circuit, and there is a problem that the sampled signal level does not always correspond to the original image information.
In order to solve such a problem, for example, Japanese Patent Publication No. 55349/1987 has suggested a circuit called correlated double sampling in which the signal level and the reference level are sampled and a difference between these levels is then taken out. However, for the purpose of realizing the correlated double sampling, it is necessary to combine the above-mentioned circuit with a plurality of sample and hold circuits and a differential amplifier, and in order to arrange them on a circuit substrate, a wide area is required. In addition, it can also be conceived that these circuits are constituted in the form of an integrated circuit, but it is difficult to constitute, in the form of one chip, the circuit for the correlated double sampling which comprises the bipolar transistor and the peripheral circuits for the CCD image pickup device 1 which comprises the MOS transistors. In consequence, the chips constituting the peripheral circuits and the wiring inconveniently increase.